System/1 Build Log
An ongoing chronology of System/1's construction, and any
other related musings.
All Build Log Entries
- 18th April, 2014 - Construction begins!
- 8th June, 2014 - Full set of register module boards assembled
- 14th June, 2014 - Populating the register file
- 20th June, 2014 (1) - Populating the register file, take 2
- 20th June, 2014 (2) - Initial register file testing
- 13th July, 2014 - Main Register File testing completed
- 13th September, 2014 - Breadboarding the clock generator
- 26th September, 2014 - Prototyping and building the ALU
- 28th September, 2014 - Fourgen and concat build
- 7th October, 2014 - Prototyping the flags register
- 19th October, 2014 - Constructing and testing the flags register
- 16th November, 2014 - Prototyping the memory interface
- 17th December, 2014 - Memory interface built
- 5th January, 2015 - Time to write about this thing!
- 17th January, 2015 - Adventures in the removal of flux residue
- 18th January, 2015 - Populating and testing the memory interface
- 7th February, 2015 - More memory interface testing
- 8th March, 2015
- 20th June, 2015 - Things are taking shape!
- 25th July, 2015 - Debugging the control unit, and running System/1's first code
- 1st May, 2016 - Starting work on a front panel
- 15th May, 2016 - In which an idea is obvious, in retrospect.
- 16th August, 2016
- 1st October, 2016
- 14th November, 2016 - Revisiting the clock and machine cycle generator design
- 1st February, 2017 - A slight interruption
- 15th August, 2017 - Building the clock board