System/1 Build Log

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An ongoing chronology of System/1's construction, and any other related musings.

17th December, 2014 - Memory interface built

This entry was backdated.

The memory interface was last seen in a cut-down form on my breadboard, so was in need of a permanent home on a real board that can be attached to the system's backplane. Before that could happen, though, I needed to decide upon a way to connect memory devices up to the bus.

My initial thoughts were for a pair of ribbon cables, one 34-way and one 40-way, to carry between them the 32-bit address and data buses and a variety of control signals along with power. However, when I started making a list of control signals to include — an address strobe, read strobe, four write strobes (one per byte), a 'wait' signal back from memory (in case I ever attach any slow devices that need to stretch the cycle timings), and an interrupt request line — it became apparent that I was going to be very tight on pins. And indeed, shortly afterwards I realised it would be nice to include a reset signal (in case any I/O devices have state that should get reset at power-on) and perhaps a signal to indicate whether the system is running code in interrupt context or user mode (in case I ever try to add a MMU of some description to the system). Add power and a few ground lines as a feeble mitigation against crosstalk and we definitely need more pins.

The Mk. II memory bus layout, therefore, uses a 34-way ribbon to carry data and power, and a 50-way ribbon to carry address and control signals with enough spare pins to add extra signals if I later decide they're needed. For now the spare pins will be tied to ground at the CPU end and used as guards between nibbles of the address.

With the bus layout decided and suitable connectors ordered (from Toby, who happen to be based about a mile away from home and are rather cheaper than Farnell for such things), it's time to sit down and build up the memory interface itself. This is a significantly denser board than those I've built to date — 20 ICs, plus decoupling caps, plus pull-down resistors on bus lines just in case, plus the connectors — and so the approach I've used so far of spacing chips out nicely along the long edge of the board and 'stitching' the power buses on the component side won't work. Instead, I'll have to fit the chips in rows across the shorter width of the board, and route power on the bottom down the middle of each column of chips.

There's also a lot more wiring to do than on previous boards; the connections between chips and to the backplane aren't too bad, although there are still quite a few of those, but then there are two 32-bit wide buses to wire up. Luckily this goes quickly enough once one gets into a rhythm, although some swearing happened when I remembered the bottom two address bits need to go not only to the bus but also the write strobe generation and single-byte readout logic. Whoops. Thankfully that omission was easy enough to correct without resorting to bodge wires.

I finally finished the wiring this evening, including a PTC in the bus power lines (an attempt to protect the ribbon cable should it get pinched between metal edges in the case) — the PTC doesn't work quite as I expected (it takes around 30 seconds to 'blow' and then still allows a good few tens of milliamps to flow), but it should do the job should the need ever arise. Now the only problem is how to clean the flux off the board, as it's incredibly sticky right now and far too densely-wired to want to risk the scrubbing-with-an-old-toothbrush approach that broke a connection on the flags board. Maybe I'll leave it as-is; something to think about over Christmas...