System/1 Build Log

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An ongoing chronology of System/1's construction, and any other related musings.

26th September, 2014 - Prototyping and building the ALU

This entry was backdated.

It's nearing the end of my little holiday, and although I've ended up splitting my time between tinkering with System/1 and various other escapades I have managed to make reasonable progress. When we last looked at the clock generator I started prototyping at the beginning of the break, we'd run out of space on the breadboard — a Sunday morning trip to Maplin didn't help, as they were out of stock on the breadboards that would extend my existing arrangement, so instead a larger one was ordered from Farnell. I also took the opportunity to stock up on various logic chips that hadn't featured in my original design but had shown themselves to be useful in my prototyping efforts. (I should mention that the original big order for parts was funded by a £100 voucher that was due to expire, and so a few sections of the design were rushed through on a 'best guess' basis to give me some idea of what I'd need!)

Once the new breadboard arrived (last Tuesday, after a fun day's ambling around Bristol with a camera on the Monday) and the existing clock generator circuit had been transplanted onto it, adding support for requesting the shorter and longer front panel operation cycles proved straightforward. To finish it off, I added another 32-clocks-long machine cycle which will be used as required to enter an interrupt context, and finally some OR gates to correctly blank off the 'bit' and 'memory' clock signals. I also changed the '4024 ripple counter (generating the 0-31 clock phase) for a pair of '161s; I'm not entirely sure that's particularly important, but I get a nagging feeling the asynchronous reset and ripple output of the '4024 might come back to haunt me otherwise.

With that all working nicely, it looks in good shape to build a board; however, I think I'll hold off on doing that until I have a few more functional units built, just in case there are any unforeseen problems. Instead, I just drew up a schematic last weekend; it looks nothing like my original notes, as they didn't include any of the required support for the front panel or interrupts (which are a relatively late addition to the system), but at least I'm happy that it stands half a chance of working now.

So onwards to something else that's reasonably fundamental to the system — the ALU. Most of this is quite straightforward (a single-bit full adder with a latch to hold the carry value between bits, and a bunch of logic operations feeding a multiplexer), but I'd like to breadboard it first to make sure I haven't made any daft errors in my schematic.

One definite change from my original notes is relates to the 74HC74 that stores the carry for the next bit. My early experiments with the clock generator underlined the problems that can crop up trying to mix asynchronous and synchronous signals, and the design I drew up when I first started thinking about a bit-serial system a few years ago used the asynchronous PRE and CLR inputs to pre-load the latch with the initial carry value during bit 0. (It should ordinarily be clear, of course, but presetting it with a 1 allows an 'increment' mode as well as making two's-complement subtraction an easy operation to support.) Instead, I think I'll add a little extra logic to switch between the initial value (during bit 0) and the latch output (during bits 1-31), and avoid the asynchronous control signals entirely.

Having made that change and built the design up on the breadboard, I wrote another set of tests to run on the mbed and compare the ALU outputs with the expected results. Everything looks good, except I don't like the sense of the carry output during a subtraction — it feels wrong to have the carry flag set when the subtraction hasn't wrapped around, somehow. I'd rather have it act as a borrow bit, which is easy enough to accomplish using a spare XOR gate, and also means it was definitely worthwhile to spend the afternoon breadboarding the design. Being happy with the final circuit, I committed it to a real board and tested it out over the latter half of this week.