Flags Register and Condition Evaluator
This board contains the flags register — in fact, two flags registers, to accomodate simple switching between 'user' and interrupt contexts — and the associated logic for evaluating condition codes in branch instructions.
Each of the two flags registers is built around a 74HC173 quad D flip-flop, with inverted versions of the LOAD_FLAGS and INT_CTX signals used to drive the enable inputs appropriately such that one is loaded when executing code in an interrupt context, and the other is loaded in 'user' context.
A 74HC157 quad 1-of-2 data selector is used to choose the appropriate set of register outputs, again based on the INT_CTX signal, and these are ANDed with the low three bits of the condition code (which will be present on the SUBOP0-SUBOP2 signals when executing a conditional jump). These three results are ORed together, and finally the result is XORed with the top bit of the condition code from SUBOP3 to provide the ability to negate the condition. This output becomes the CONDITION_MET signal for the control unit to consume.
The flags themselves are derived from the R bus and CARRY_OUT; the 'less-than-zero' and 'carry' flags are just these two signals latched directly, so that they represent the high bit and final carry state of the most-recent operation to have been performed with LOAD_FLAGS set. The 'zero' bit is derived in a slightly more complex fashion; basically the R input is ORed with the current state of the bit, such that any incoming 1 sets the bit and leaves it set regardless of later 0s. Of course, this requires that the bit is somehow reset at the start of each operation; to do this, the existing state of the bit is ANDed with an OR of all five bits of the CP clock phase counter, so that bit 0 in each 32-bit word is effectively latched into the flags register untouched. This gives us an 'at-least-one-1-present' bit, which is then inverted to give a true 'zero' bit for use by the conditon evaluator.